1. Field of the Invention
This invention relates to electronic circuits, and more particularly, clock circuits for providing timing signals.
2. Description of the Related Art
As the operating speed of computer processors has increased, the operating speeds of system boards implementing these processors has increased as well in order to eliminate or reduce the effects of bottlenecks. With the clock speeds of processors approaching 1 GHz it is not uncommon for system boards to operate at a clock speed exceeding 100 MHz.
Source synchronous I/O may eliminate or minimize problems that may occur when the data transfers a synchronized to a single system clock. Source synchronous I/O may allow more flexibility in designing system boards, as the clock speed used by source synchronous I/O lines may scale with the processor clock speeds. Furthermore, the use of source synchronous I/O may eliminate length constraints on signal lines.
In a source synchronous data transfer, the device transferring the data may also generate and transfer a clock signal along with the data. The receiving device may receive the clock signal from the source, and may thereby synchronize the data transfer with the received clock. This may allow the clock lines between two devices to be much shorter in length, thereby eliminating much of the clock skew that may otherwise occur.
While source synchronous I/O may be useful in minimizing or eliminating the clock skew problems that occur when data transfers are synchronized to a single system clock, other problems may arise. One such problem may be noise, as the increased number of clock signals present on the board may create unwanted electromagnetic noise. Such noise may cause problems with some source synchronous clock signals, such as clock jitter. The problems that arise with source synchronous I/O may result in the need to repeat some data transfers. Repeating a data transfer in some cases may require a reset to the device to which the data was to be transferred. This may result in a severe performance penalty for the system in which the source synchronous device is implemented.